Python can also be used as a Hardware Description Language (HDL), allowing for the creation of complex designs using high-level programming concepts. This makes the design process faster and less error-prone than traditional HDLs.
MyHDL is a remarkable open-source Python package that helps you to transform Python to silicon by using it as a hardware description and verification language. This package provides an ideal solution for high-level modeling, with Python's power and clarity, enabling efficient solutions to even the most complex modeling problems. It is also outstanding for rapid application development and experimentation.
The key idea behind MyHDL is the use of Python generators to model hardware concurrency. MyHDL generators enable resumable functions similar to always blocks in Verilog and processes in VHDL, leading to the modeling of the hardware module as a function that returns generators. This methodology provides features that support hierarchy, named port communication, arrays of instances, and conditional instantiation easily.
MyHDL also offers classes that implement traditional hardware description concepts that comprise a signal class to support communication, a class to support bit-oriented operations, and a class for enumeration types. The built-in simulator in MyHDL runs on top of the Python interpreter, supporting waveform viewing by tracing signal changes in a VCD file.
With MyHDL, Python unit test frameworks can be used on hardware designs, which is still uncommon in the hardware design world. Besides, MyHDL serves as a hardware verification language for Verilog designs, where one can utilize co-simulation with traditional HDL simulators for hardware verification.
MyHDL designs can be converted to Verilog or VHDL, subject to some limitations. This process provides a path into a traditional design flow, including synthesis and implementation. As a result, the conversion limitations apply only to code inside generators. Python's complete power can be leveraged outside the generators without compromising convertibility, and the converter automates a variety of tasks that can be challenging in Verilog or VHDL, such as automated handling of signed arithmetic issues.
The key idea behind MyHDL is the use of Python generators to model hardware concurrency. MyHDL generators enable resumable functions similar to always blocks in Verilog and processes in VHDL, leading to the modeling of the hardware module as a function that returns generators. This methodology provides features that support hierarchy, named port communication, arrays of instances, and conditional instantiation easily.
MyHDL also offers classes that implement traditional hardware description concepts that comprise a signal class to support communication, a class to support bit-oriented operations, and a class for enumeration types. The built-in simulator in MyHDL runs on top of the Python interpreter, supporting waveform viewing by tracing signal changes in a VCD file.
With MyHDL, Python unit test frameworks can be used on hardware designs, which is still uncommon in the hardware design world. Besides, MyHDL serves as a hardware verification language for Verilog designs, where one can utilize co-simulation with traditional HDL simulators for hardware verification.
MyHDL designs can be converted to Verilog or VHDL, subject to some limitations. This process provides a path into a traditional design flow, including synthesis and implementation. As a result, the conversion limitations apply only to code inside generators. Python's complete power can be leveraged outside the generators without compromising convertibility, and the converter automates a variety of tasks that can be challenging in Verilog or VHDL, such as automated handling of signed arithmetic issues.
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