Signs is a logic synthesis and gate level simulation software designed to help users generate efficient circuits for digital systems. It streamlines the process of designing logic circuits by offering automatic optimizations, scalable features, and built-in gate-level simulation capabilities.
Signs is a comprehensive tool designed for logic synthesis and gate level simulation. The project hosts an array of impressive features that include the synthesis of RTL-style VHDL circuit descriptions and a dynamic graphical netlist viewer. Signs also offers support for various formats such as VHDL, ISCAS, and limited backing for BLIF, Verilog and EDIF netlists. It also comes equipped with multiple true value and fault simulators, and a combinational ATPG for circuit testing.
One of the prominent features of Signs is its ability to be utilized through a GUI mode, a pure command line mode, and is fully scriptable in JavaScript and Ruby. Additionally, Signs is platform-independent due to being written in Java. While the project aims to be VHDL93 compliant, it currently supports a VHDL Subset. And offers limited support for non-synthesizable VHDL code, useful for testbenches.
Signs presents various other features such as the synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6, dynamic graphical netlist viewer with annotations, VHDL netlist output to file, input and output of netlists in ISCAS benchmark format, and a gate level true value simulator with event-based and bit-parallel options.
Alongside these, Signs has multiple fault simulators, input and output of pattern lists in WGL format, ATPG based on Implication Graph and PODEM for combinational circuits, and limited support for Verilog and EDIF netlists. Additionally, Signs is fully scriptable in Rhino with support for JavaScript and JRuby.
Signs has an integrated environment, including source code and netlist structure tree views, build system, compilers, and editors with syntax highlighting. The latest revision focuses primarily on bug fixes but also includes feature improvements such as enhanced test bench support, updated netlist and simulator views, and improved context handling for faster elaboration of bigger designs. The intermediate representation layer has also undergone an overhaul internally, ensuring proper representation of intermediate objects as a tree.
One of the prominent features of Signs is its ability to be utilized through a GUI mode, a pure command line mode, and is fully scriptable in JavaScript and Ruby. Additionally, Signs is platform-independent due to being written in Java. While the project aims to be VHDL93 compliant, it currently supports a VHDL Subset. And offers limited support for non-synthesizable VHDL code, useful for testbenches.
Signs presents various other features such as the synthesis of RTL-style sequential VHDL process descriptions according to IEEE Std 1076.6, dynamic graphical netlist viewer with annotations, VHDL netlist output to file, input and output of netlists in ISCAS benchmark format, and a gate level true value simulator with event-based and bit-parallel options.
Alongside these, Signs has multiple fault simulators, input and output of pattern lists in WGL format, ATPG based on Implication Graph and PODEM for combinational circuits, and limited support for Verilog and EDIF netlists. Additionally, Signs is fully scriptable in Rhino with support for JavaScript and JRuby.
Signs has an integrated environment, including source code and netlist structure tree views, build system, compilers, and editors with syntax highlighting. The latest revision focuses primarily on bug fixes but also includes feature improvements such as enhanced test bench support, updated netlist and simulator views, and improved context handling for faster elaboration of bigger designs. The intermediate representation layer has also undergone an overhaul internally, ensuring proper representation of intermediate objects as a tree.
What's New
Version 0.6.3: N/A