The Verilog Parser is a comprehensive grammar tool that uses Perl to analyze and parse Verilog code, providing an efficient and reliable way to validate, verify and communicate design specifications.
The Hardware::Verilog::Parser is an alpha release Perl module that provides the complete grammar necessary to parse any Verilog code. This allows users to create customized Perl scripts that can execute specific functions on Verilog code.
One example of this is the module Hierarchy.pm which uses the module to overload the grammar rule for module instantiations. This modification can then print out all instance names within the parsed file. This feature can be helpful in creating an automatic build script or a graphical hierarchical browser for a Verilog design.
While this module is currently in alpha release and subject to change, users can still take advantage of its functionality. The module can be easily implemented by using the provided SYNOPSIS code. Users simply need to include the Hardware::Verilog::Parser module and create a new parser object. They can then specify the input filename and run the script according to their custom function.
Overall, the Hardware::Verilog::Parser module can be a valuable tool for those working with Verilog code. Bug reports are welcomed to help improve its performance and functionality.
One example of this is the module Hierarchy.pm which uses the module to overload the grammar rule for module instantiations. This modification can then print out all instance names within the parsed file. This feature can be helpful in creating an automatic build script or a graphical hierarchical browser for a Verilog design.
While this module is currently in alpha release and subject to change, users can still take advantage of its functionality. The module can be easily implemented by using the provided SYNOPSIS code. Users simply need to include the Hardware::Verilog::Parser module and create a new parser object. They can then specify the input filename and run the script according to their custom function.
Overall, the Hardware::Verilog::Parser module can be a valuable tool for those working with Verilog code. Bug reports are welcomed to help improve its performance and functionality.
What's New
Version 0.13: N/A