HDLmaker is a FPGA development system that generates Verilog/VHDL code.
HDLmaker is a powerful tool for creating Verilog designs that simplifies the development of complex FPGA designs and PC boards. With HDLmaker, you can write hierarchical Verilog code, generate retargetable IO pad rings, create all necessary scripts and Make files, and support multi-language projects. Additionally, it can also convert PCB netlists into VHDL and Verilog and generate SCALD and PADS PCB board netlists, as well as schematics in Postscript format.
One of the best features of HDLmaker is its portability between FPGA families and CAE tools, making it easy to reuse HDL code and format the designs as needed. It also converts HDLmaker, Verilog, and VHDL files into fully hyperlinked HTML for easy navigation.
HDLmaker has a variety of key features that make it stand out among other Verilog design tools. It writes hierarchical Verilog code and can output to either Verilog or VHDL (VHDL support has been deprecated). It supports mixed language development and can generate PC board netlists in both PADS PCB and SCALD formats.
HDLmaker supports the most popular FPGAs, including Xilinx Virtex4, Virtex2P, Virtex2, VirtexE, Virtex, Spartan3, Spartan2, 4000E, 4000EX, 4000XL, 5200, and 9500, as well as Altera Stratix. It also supports the most popular synthesizers, including Synplify, Xilinx XST, Altera, Synopsys Design Compiler, and Precision. Additionally, it supports most simulators, including Fintronics Finsim, Cadence Verilog XL, Cadence NC-SIM, Model Technologies (VHDL and Verilog), and Synopsys VCS.
HDLmaker also generates an HTML version of the design with hyperlinks from all source files to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax-colored for easy readability.
In the latest release, HDLmaker has added several new features, including insert_compare, which inserts a module with a compare wrapper around it, and HDLMAKER_ALLOW_SUB variable. It also added xst_directive, floorplanning support for multipliers and block RAMs, and new XST constraints. Additionally, it has improved DDR IO support, including differential DDR, and Xilinx project support, as well as better ModelSim support.
HDLmaker now supports initial values of HDLmaker variables that can be passed in from the command line or a file, better comment support, more flexible #clock statement, and comments in pin files. It also supports Xilinx ISE 6.1, Virtex2P, Precision, and large project support. HDLmaker now operates across multiple directories and supports Virtex2, Spartan2, Spartan2E, and Altera Stratix. It also has multilanguage project support, allowing you to embed VHDL entities into Verilog files and Verilog modules into VHDL files.
One of the best features of HDLmaker is its portability between FPGA families and CAE tools, making it easy to reuse HDL code and format the designs as needed. It also converts HDLmaker, Verilog, and VHDL files into fully hyperlinked HTML for easy navigation.
HDLmaker has a variety of key features that make it stand out among other Verilog design tools. It writes hierarchical Verilog code and can output to either Verilog or VHDL (VHDL support has been deprecated). It supports mixed language development and can generate PC board netlists in both PADS PCB and SCALD formats.
HDLmaker supports the most popular FPGAs, including Xilinx Virtex4, Virtex2P, Virtex2, VirtexE, Virtex, Spartan3, Spartan2, 4000E, 4000EX, 4000XL, 5200, and 9500, as well as Altera Stratix. It also supports the most popular synthesizers, including Synplify, Xilinx XST, Altera, Synopsys Design Compiler, and Precision. Additionally, it supports most simulators, including Fintronics Finsim, Cadence Verilog XL, Cadence NC-SIM, Model Technologies (VHDL and Verilog), and Synopsys VCS.
HDLmaker also generates an HTML version of the design with hyperlinks from all source files to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax-colored for easy readability.
In the latest release, HDLmaker has added several new features, including insert_compare, which inserts a module with a compare wrapper around it, and HDLMAKER_ALLOW_SUB variable. It also added xst_directive, floorplanning support for multipliers and block RAMs, and new XST constraints. Additionally, it has improved DDR IO support, including differential DDR, and Xilinx project support, as well as better ModelSim support.
HDLmaker now supports initial values of HDLmaker variables that can be passed in from the command line or a file, better comment support, more flexible #clock statement, and comments in pin files. It also supports Xilinx ISE 6.1, Virtex2P, Precision, and large project support. HDLmaker now operates across multiple directories and supports Virtex2, Spartan2, Spartan2E, and Altera Stratix. It also has multilanguage project support, allowing you to embed VHDL entities into Verilog files and Verilog modules into VHDL files.
What's New
Version 7.4.4: N/A