FSMDesigner4 is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated HDL generation.
Version: 1.2FSMDesigner4 is a C++ based implementation for a Finite State Machine (FSM) design tool with integrated Hardware Description Language (HDL) generation. It uses the Simple-Moore FSM model. This guarantees an efficient design for fast complex control circuits.
Operating System: Linux
Here are some key features of "FSMDesigner":
· Graphical design of FSMs including:
· states, transitions, conditions
· supports hierarchies
· links, joins, global transitions
· Support for automatic default transitions (xrest function)
· Validation of FSMs
· Save & load of FSMs in well defined XML files
· Generation of RTL HDL output
· Fully scriptable in Python or TCL
· Modern GUI with all features expected (undo, redo, ...)
· Simulation mode support
· Supports Linux, easily portable to other OS
· Table based data manipulation
What's New in This Release:
· Implemented SVG export, printing should work, improved state mnenonic map (include color), implement mnenonic maps for complete projects, and several small bugfixes.
· Additionally, version 1.2 adds System Verilog Assertions as an option for the HDL output thus supporting efficient verification including coverage analysis.