LogicSim is a cost-effective and simple Verilog simulator that enables ASIC and FPGA design verification. It features a robust and intuitive graphical interface that enables quick Verilog design simulation.
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Our system has scanned the download for viruses, and we suggest that you also check the files before installation. The version of LogicSim you are about to download is 3.3, and the download will be provided as is, with no modifications or changes made on our end.