SystemC Netlist is a software simulation platform that provides a comprehensive solution to design, model, and simulate electronic systems. It helps the designers to create high-level designs of complex systems with higher accuracy and scalability, without sacrificing performance.
In this software review, we will be discussing SystemC::Netlist, a Perl module used for interconnect information within a whole design database. To make use of this module, simply use the SYNOPSIS code:
use SystemC::Netlist;
# See Verilog::Netlist for base functions
$nl->autos();
$nl->exit_if_error();
The SystemC::Netlist classes are parallel to those in Verilog::Netlist, so any documentation required can be found there.
The database is composed of files, which contain the text read from each file. Within those files are modules, which are individual blocks that can be instantiated, also known as designs in Synopsys terminology. Modules have ports, which are the interconnection between nets in that module and the outside world. In addition, modules also have nets (or signals) which interconnect the logic inside that module.
Another important feature of modules is their ability to instantiate other modules. When a module is instantiated, it forms a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.
Each of these types, files, modules, ports, nets, cells, and pins have a class. For example, SystemC::Netlist::Cell has the list of SystemC::Netlist::Pin(s) that interconnect that cell.
Overall, SystemC::Netlist is a useful Perl module for managing and maintaining interconnect information within a design database.
use SystemC::Netlist;
# See Verilog::Netlist for base functions
$nl->autos();
$nl->exit_if_error();
The SystemC::Netlist classes are parallel to those in Verilog::Netlist, so any documentation required can be found there.
The database is composed of files, which contain the text read from each file. Within those files are modules, which are individual blocks that can be instantiated, also known as designs in Synopsys terminology. Modules have ports, which are the interconnection between nets in that module and the outside world. In addition, modules also have nets (or signals) which interconnect the logic inside that module.
Another important feature of modules is their ability to instantiate other modules. When a module is instantiated, it forms a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.
Each of these types, files, modules, ports, nets, cells, and pins have a class. For example, SystemC::Netlist::Cell has the list of SystemC::Netlist::Pin(s) that interconnect that cell.
Overall, SystemC::Netlist is a useful Perl module for managing and maintaining interconnect information within a design database.
What's New
Version 1.310: N/A