A Perl software tool that offers full grammar for parsing VHDL code.
For instance, Hierarchy.pm uses Hardware::Vhdl::Parser to modify the grammar rule for component instantiations, allowing for the printing of instance names in the parsed file. This feature is particularly useful for creating an automatic build script or a graphical hierarchical browser of a VHDL design.
Keep in mind that Hardware::Vhdl::Parser is currently in beta release and all code may be subject to change. We welcome bug reports to ensure a seamless user experience.
To get started, simply employ the Hardware::Vhdl::Parser module and use the provided function to assign a filename to the parser. Say goodbye to the tedium of VHDL code parsing and let Hardware::Vhdl::Parser handle the job for you.
Version 0.12: N/A