HDLmaker is a Verilog/VHDL code generator and FPGA development system.
Version: 7.4.4HDLmaker is a tool for generating Verilog designs. HDLmaker simplifies the development of complex FPGA designs as well as PC Boards by performing the following tasks:
License: BSD License
Operating System: Linux
· Writes hierarchical Verilog code
· Generates retargetable IO pad rings
· Generates all of the necessary scripts and Make files
· Supports mulitlanguage projects
· Converts PCB net lists into VHDL and Verilog
· Generates SCALD and PADS PCB board netlists
· Generates Schematics in Postscript format
· Designs are portable between FPGA families and CAE tools
· Simplifies the reuse of HDL code
· Converts HDLmaker, Verilog and VHDL files into fully hyper linked HTML
Here are some key features of "HDLmaker":
· Writes Hierarchical Verilog.
· Output can be targeted to either Verilog or VHDL (VHDL support has been deprecated).
· Supports mixed language development.
· Generates PC board netlists in both PADS PCB and SCALD formats.
· Generates Schematics in Postscript format.
· Supports the most popular FPGAs
· Xilinx Virtex4,Virtex2P, Virtex2,VirtexE,Virtex, Spartan3, Spartan2,4000E,4000EX,4000XL,5200,9500, Altera Stratix
· Supports the most popular synthesizers
· Xilinx XST
· Synopsys Design Compiler
· Supports most simulators
· Fintronics Finsim
· Cadence Verilog XL
· Cadence NC-SIM
· Model Technologies (VHDL and Verilog)
· Synopsys VCS
· HTML Generation
· HDLmaker generates an HTML version of the design with hyper links from all source files to generated files and from all component instances to the component's module. Verilog and VHDL HTMLized are also syntax colored.
What's New in This Release:
· insert_compare, Inserts a module with a compare wrapper around it
· Added HDLMAKER_ALLOW_SUB variable
· Added xst_directive
· Floorplanning support for Multipliers and Block RAMs
· New XST constraints
· Improved DDR IO support including differential DDR
· Improved Xilinx project support
· Virtex4 Support
· Better ModelSim support. Creates three command files, foo_compile_mt.cmd to compile the modules, foo_i_mt.cmd for interactive use, and foo_batch_mt.cmd for batch simulation.
· Initial values of HDLmaker variables can be passed in from the command line or from a file
· Better comment support
· More flexible #clock statement
· Comments in pin files
· Support for Xilinx ISE 6.1
· Support for Virtex2P
· Support for Precision and ModelSim added
· Large Project Support, HDLMaker now operates across multiple directories
· Virtex2, Spartan2 and Spartan2E support added
· Altera Stratix support added
· Multilanguage project support. Can embed VHDL entities into Verilog files and Verilog modules into VHDL files.